Introduction

Handshake Technology is a design methodology and associated toolset for clockless, self-timed circuits. The familiar global clock used in traditional very-large-scale-integration (VLSI) design is replaced with a system of request and acknowledgement signals or handshakes. Haste is Handshake Solutions' dedicated design entry language supporting CSP concepts like parallelism and channel communication. It is similar to the well-known C programming language and comparable with behavioral Verilog or VHDL.

Goal of Project

The goal of this project is to extend the Haste language with assertions, and a tool that statically analyzes these assertions at Haste level. Assertions can for example be 'absence of deadlock', 'guaranteed progress', or simple ‘invariants’. The tool can be homegrown or it can involve existing tools and models, e.g. SPIN (as the semantics of Promela resembles Haste semantics quite nicely, http://spinroot.com), Microsoft Slam Project for concurrent processes, or environment modeling (e.g. http://www.iccd-conference.org/proceedings/2002/17000070.pdf)

Candidate

This is a Master’s Thesis project in Computing Science. The ideal candidate has a background in formal methods.

  1. 2005-04-10T00:00:00.0000000-07:00Student project application form