Introduction

Handshake Technology is a design methodology and associated toolset for clockless, self-timed circuits. The familiar global clock used in traditional very-large-scale-integration (VLSI) design is replaced with a system of request and acknowledgement signals or handshakes. Haste is Handshake Solutions' dedicated design entry language supporting CSP concepts like parallelism and channel communication. It is similar to the well-known C programming language and comparable with behavioral Verilog or VHDL.

One of the strengths of the Handshake Technology design flow as developed by Handshake Solutions is that for its implementation in VLSI it can work with generic standard-cell libraries that do not contain any special asynchronous cells. While this makes adoption of the technology easy, it is also a limitation towards maximum exploitation of the technology advantages.

Goal of Project

It is the purpose of this work to define a standard-cell library extension for handshake circuits and to quantify its benefits in terms of area, energy and performance. Elements that will be considered for special cells are those that rely on analog properties for their operation, such as arbiters and delay elements, and asynchronous sequential elements, such as generalized C-elements. Testable versions of these cells should also be covered.

Candidate

This is a Master's Thesis project in Electrical Engineering or Computing Science. The ideal candidate has a background in VLSI, logic optimization, SPICE, Place and Route.