Are you ready for a new way of thinking?


Find out at our free-to-enter Handshake Technology web-based seminars.


Handshake Technology is a revolutionary new approach that solves power and integration problems while making your design more robust. The only ready-to-use self-timed design methodology available today, it lets you access these key benefits of clockless technology in a reliable and reproducible manner that is perfectly adapted to commercial IC design.


The webinars provide an introduction to the technology as well as the design tools and services that back it up. These webinars include demonstrations of some of the key tools.

 

Recorded Webinars

You can view the following recorded webinars on-line at your own convenience:

An Introduction to Handshake Solutions
Where will you take Handshake Technology? (duration: 30 min)

Handshake Solutions Design Tools (TiDE)
Overview and demonstration of the Handshake Solutions design tools (TiDE). This webinar addresses design, simulation, and optimization of designs in the high-level language Haste. We also demonstrate the automatic synthesis from Haste into a Verilog netlist. In addition we show the integration of Handshake Solutions design tools into standard EDA flows and our Design-for-Test solution. (duration: 40 min)

The ultra low-power HT80c51 microcontroller
In this presentation we will give an overview of the HT80c51 and address the features, interfaces, peripheral units, and characterization of the HT80c51. (duration: 25 min)

The ARM996HS, The first licensable, clockless 32-bit processor core
In this presentation we will give an overview of the ARM996HS processor core and address the features, interfaces, and characterization. (duration: 15 min; screen size: 1280x1024)

 

Live Webinars

We also organize free-to-enter live webinars about different topics. During these webinars we give demonstration of new products and new features and you can adress questions to our technical staff.

 

Scheduled webinars:

 

Currently there are no live webinars scheduled.