Clockless design is creating huge interest in the industry. As companies are becoming aware that the unique benefits of clockless ICs are now available in a robust, commercially viable methodology, they are increasingly looking for designers who have experience of clockless design. To help universities meet this demand, we’re making our tried-and-tested design flow, tool set and Haste design-entry language available for academic purposes!

 

What you get

Universities who take up this offer will have access to our complete design environment (TiDE). So students will be able to learn clockless design using exactly the same tools as commercial designers use to develop real-life products. However, universities will not have a license to commercially manufacture their designs.

Universities can currently choose between the following two packages:

 

What people are saying

"The design language Haste has proven a perfect vehicle for the design of highly parallel VLSI systems" said Prof. Kees van Berkel of Eindhoven University of Technology. Since 1997, prof van Berkel has been using the academic package in a 'VLSI programming' course, which covers clockless circuit design steps from the gate-level to the design of a simplified DLX processor using Haste. Emphasis is given to the quantitative aspects of VLSI programming, such as die area, power consumption, and throughput of Haste programs.

 

Networking

To share information, research papers, experiences, best practices, course exercises, and other insights with other members of the Academic Program join the Handshake Solutions Academic Network Group (Google Group).

  1. 2008-08-05T00:00:00.0000000+02:00Academic Program Members
  2. 2008-05-08T00:00:00.0000000+02:00HS Academic Network Group

 

 

How you get it

For universities and academic research centers located within Europe, our tools are available for licensing through Europractice.

For universities and academic research centers located outside of Europe, please use the procedure described here.