Design entry within TiDE is carried out via Haste, Handshake Solutions’ proprietary high-level programming language. A Haste program is synthesized to a Verilog netlist based on cells from your preferred standard-cell library in two stages.

First, htcomp translates the Haste code into an intermediate Handshake Circuit in a transparent, syntax-directed process. Then you can use htmap to map the Handshake Circuit to a structural Verilog netlist and for initial circuit-level optimization.

Simulation and analysis

TiDE supports simulation of designs at a number of levels. A Haste program can be compiled into behavioral Verilog or System-C model for quick functional simulation in combination with existing chip-level and system-level test benches using industry-standard simulators. In addition, both pre- and post-layout simulations of the structural Verilog netlist can be carried out where more detailed performance data is available based on the standard-cell library used.

The simulation results can be reviewed and analyzed by thirdparty viewers, or can be interactively analyzed at the Haste source level with htview.

The htcover tool analyzes the results collected from one or more gate-level simulation runs and reports the functional code coverage statistics, including statement and expression coverage. The latter keeps track of all values of the expressions and can be used for test bench qualification. Performance analysis is facilitated by htprof , which is an interactive tool for critical path identification, including a reference to the originating Haste source code.

FPGA prototyping

The htmap tool can also map the intermediate Handshake Circuit to a synchronous RTL netlist by selecting a clocked handshake implementation. Because this netlist is synchronous, you can map this on an FPGA, using any commercially available FPGA mapping tool from vendors like Xilinx, Altera or Synplicity.