This means that only those parts of a system actively involved in task execution draw power, reducing standby power consumption to zero and extending battery lifetimes. What’s more, individual functions don’t have to wait for the next clock pulse, enabling immediate response to exceptional events.

The handshake signaling approach also allows a truly plug-and-play method of integrating IP from various sources. Because they exhibit no ground bounce, Handshake Technology functions can be quickly and easily combined with clocked logic, analog, RF or memory blocks to meet the exact requirements of your system.

And by implementing a rigorous approach we’ve solved the problems traditionally associated with asynchronous technologies. For example, Handshake Technology supports FPGA prototyping and scan-test for complete Design-for-Test solutions. Now you really can bring products to market using self-timed circuitry.

Moreover, bringing discipline to clockless design has allowed us to develop all the machinery required for the creation of arbitrarily complex ICs. This includes a high-level design language, called Haste, similar to C and behavioral Verilog that speeds the design process via a Silicon Compiler and Netlist Generator.

Handshake Technology also incorporates a design flow based on standard cell libraries with no dedicated asynchronous cells required and is compatible with standard ‘synchronous’ tools for technology mapping and timing analysis.