Haste is Handshake Solutions high-level design language developed specifically for the design-entry stage of clockless IC design. Similar to C and comparable with behavioral Verilog or VHDL, it is easily picked up by anyone familiar with traditional IC or software design.

Achieving a higher abstraction level than RTL level VHDL or Verilog, Haste enables the same functionality to be created with much smaller codes. Depending on the final application, some customers have reported code size savings of around a factor of 10.

A behavioral language inspired by Communicating Sequential Processes (CSP)^[1], amongst other things Haste supports:

• Variables
• Synchronized message passing via channels
• Inter and intra process parallelism
• Explicit sharing of resources
• Arbitration
• Datapath operators
• Conditional and iteration operators
• Procedure and function abstractions, etc
• Instantiation of on-chip memories (RAMs and ROMs) and register files
• Easy interfacing to synchronous domains through specific Haste constructs for
• waiting for events or levels on signals
• reliable sampling of signals.

^{[1] Introduced by Tony Hoare in his seminal 1978 paper in Communications of the ACM}

1. 2006-02-08T00:00:00.0000000+01:00Haste Manual