Highlights

• Support for Cadence-only flow
• DfT area significantly reduced
• Ready for 65 nm and beyond
• Improved optimizations for area and speed
• Improved support for top-level designs

Support for Cadence-only flow
With TiDE release 5.2, Handshake Solutions has further simplified the interaction between the TiDE design flow and Cadence tools including Cadence ETS, Cadence Encounter and RTL Compiler. Working closely with Cadence this move makes it even easier for designers to incorporate Handshake Solutions IP. This is especially true for those companies who have selected Cadence as their single EDA tool supplier.

DfT area significantly reduced
Scan-chain insertion increases area in both synchronous and asynchronous designs. With an updated scan algorithm, TiDE 5.2 ensures overall design area is significantly reduced compared to earlier TiDE releases. This means clockless circuits can now be smaller than the same effective implementation in a synchronous design, with the rule-of-thumb being asynchronous and synchronous designs are roughly within a 10% range.

Ready for 65 nm and beyond
As feature sizes decrease, we are all aware that more advanced analysis techniques are required. Signal integrity (SI) and delay fault testing are issues that both synchronous and asynchronous designs struggle with – specifically at 65 nm and beyond. TiDE 5.2 offers an integrated solution to identify and resolve these issues.

Improved optimizations for area and speed
The completely automatic TiDE 5.2 flow effectively treats the datapath as a ‘synchronous’ module. This provides a better match between clockless circuitry and standard (synchronous) tools and enables synchronous constraints to be set allowing explicit setup and hold-time checking. So instead of the segmented optimization used in previous TiDE versions, the complete datapath can now be fully optimized. The result, standard EDA tools can be used to their full optimization potential, leading to smaller, faster circuits.

Improved support for top-level designs
The new release includes an updated htpost tool that can work directly on the top-level design. It automatically detects all inter-module relations and generates a single constraints file for the complete design. This decreases the chance of introducing errors, greatly simplifies the inclusion of memories and synchronous blocks, and reduces the number of manual steps.

1. 2008-01-24T00:00:00.0000000+01:00TiDE 5.2 News update