Highlights

• New tool to measure code coverage
• Layout flow for Synopsis back-end tools
• Optimized Design-for-Test (DfT) flow

Coverage tool

This new, interactive tool (htcover) measures and analyzes the code coverage of a Haste design i.e. how much of the Haste code has been executed. It allows you to assess the quality of your test bench.

To give you the most help in improving your test bench, the tool gives three measurements expressed as a percentage.

• Statement coverage: a statement is covered if it has been executed at least once
• Handshaked expression coverage: a handshaked expression is covered if every bit has been used to communicate 0 and 1
• Wire expression coverage: a wire expression (an expression with no associated handshake wires) is covered if every bit has been 0 and 1

Synopsis layout flow

This release includes a layout flow based on the Synopsis® Astro™ and Physical Compiler® tools, following on from the introduction of support for the Cadence® Encounter™ flow in release 4.2.0.

Laying out Haste designs requires some special attention to ensure the final circuit works correctly. To make this easier, we offer an example flow for both the Astro and Physical Compiler tools. This is a very simple layout flow that addresses all Haste specific issues and provides solutions. You can use it as a starting point for your own layout flow or incorporate some parts into your existing, standard layout flow.

Optimized Design-for-Test (DfT) flow

We’ve considerably extended the multiplexer-based test flow introduced in release 4.2 with several new optimization techniques. This makes possible big improvements in chip area while leaving the design fully testable. The new optimizations lead to:

• Fewer test multiplexers
• Better ‘color’ balancing
• Larger scan segments in control, reducing wires between control and data path

The end result is a smaller netlist that is easier to route.