Highlights

• Faster circuits
• Improved layout support
• Better user interfaces

Faster circuits

As circuit speed becomes more and more important, in the TiDE v4.4 flow we introduce several specific options that enable to user to make the trade-off between speed and design area. Although the exact gain in performance is design specific, designs that are compiled with the speed optimisations enabled in htmap and htpost are typically between 5% and 10% faster.

Htmap speed flow

This option enables several peephole optimisations, which result in a circuit implementation that is faster but potentially less efficient in terms of area and power. Most of the optimisations aim to improve the performance of pipeline designs, but other types of designs may also benefit from these optimisations.

Speed improvements in the Design Compiler® flow

Htpost has been extended with several options that enable the generation of faster circuits. As PKS will be phased out by Cadence, this new functionality has been developed only for Synopsys Design Compiler.

The basic principle of the htpost speed flow is better constraining the design. That way, Design Compiler is no longer only focussed on design area, but also in design speed.

The main difficulty when constraining an asynchronous design is that there is no central clock and therefore there is no clear speed target for each of the logic blocks. TiDE v4.4 introduces support for double Design Compiler runs to circumvent this problem. The first Design Compiler run is used to derive realistic constraints. The second Design Compiler run optimises the constrained design.

Improved layout support

Creating a layout for Haste asynchronous designs requires some special attention to ensure the final circuit works correctly. To make this easier TiDE now contains two example layout flows: for Cadence® Encounter™ and PKS™ and for Synopsis® Astro™ and Physical Compiler®. Those are very simple layout flows that address all Haste specific issues and provide solutions. You can use them as a starting point for your own layout flow or incorporate selected parts into an existing, standard layout flow.

The layout flow for Synopsys Astro/Physical Compiler was already included in the TiDE v4.3 release. However, it now has been updated to support several important features that were introduced in SP3 and SP5 of Astro 2004.12. This enables better delay tuning and therefore potentially faster circuits.

The layout flow for Cadence Encounter/PKS was only available on request. This flow has gone through a major revision step and is now part of our standard delivery package.

Better user interfaces

The user interfaces of both htview and htcover have been improved. Better usage of colours and text attributes make it easier to recognise what’s on the screen. Both tools now also support the display of enum types. This makes it easier to interpret displayed values.

In htview the cursors can now snap to selected value transitions, or actions and also the scroll and zoom facilities have been improved to make it easier to manoeuvre through the events.

Htcover now also supports selection of items by clicking on the source code and the improved sorting capabilities make it easier to pinpoint weak spots in the coverage of the test bench.