Highlights

• New Design-for-Test approach
• Improved scan insertion
• Easier test integration
• Integrated layout support

New Design-for-Test approach

To make bridge-fault testing and post-production failure analysis easier, we’ve introduced a new two-step clockless Design-for-Test (DfT) approach. Scan-chain insertion is still carried out before layout using htscan. However, a new tool htremodel is used to generate remodel files. This allows post-layout automatic test pattern generation (ATPG), establishing a closer match between test patterns and the actual silicon.

Improved scan insertion

TiDE 5.0.0 features an improved scan insertion algorithm. Firstly, a new ordering algorithm delivers higher layout density, performance and yield. Secondly, we’ve introduced a new optimization algorithm that reduces the number of multiplexers required for testing.

Easier test integration

TiDE 5.0 scan flow offers several new features to make it easier to integrate Haste blocks into larger (synchronous) designs. These include CTL support, anti-skew latch insertion, reset isolation, clock isolation, and top-level pattern generation.

Integrated layout support

Layout plays an increasingly dominant role on circuit timing as feature sizes decrease. Therefore, we’ve further enhanced layout support. TiDE 5.0.0 contains three example layout flows for the Cadence^® Encounter™, Magma^® Blast Fusion^® and Synopsys^® Galaxy™ digital IC design platforms.. In addition, thanks to the new DfT approach, the layout process is now fully integrated into the TiDE flow.