Highlights

• Profiler tool (New)
• SystemC modeling
• eXtreme delay tuning (XDA)
• Improved Cadence^® Encounter™ / PKS layout flow
• New and updated documentation

Profiler tool (New)

The new Handshake Technology profiler (htprof) is an interactive performance analysis tool. It identifies the slowest path between two signal transitions at a given time. Its output reports are based on simulation traces in VCD (Value Change Dump) format, which can be generated by any standard Verilog simulator.

SystemC modeling

As of release 5.1, htcomp now offers the option to generate a SystemC model from a Haste program. This is useful for verification of the Haste design as part of a complete system that has also been modeled in SystemC. The SystemC model allows the creation of an executable specification of a (complex) system that doesn’t require a Verilog simulator.

Extreme delay tuning (XDA)

Extreme delay tuning (XDA) is a new option for managing relevant delay paths in the controller. It enables more accurate measurement of control delays, leading to faster circuits with no compromise on safety.

ImprovedCadence^® Encounter™ / PKS layout flow

In TiDE 5.1.0, the Cadence^® Encounter™ / PKS layout flow has been completely revised. Reports are now generated automatically while new configuration files make it easier to find design- or technology-specific parts. In addition, the brand new tool htrebuffer addresses transition violation in the controller.

New and updated documentation

TiDE 5.1 comes with a new Haste Cookbook, which presents a sample approaches for optimizing Haste designs. It based on real-life examples and the experiences of designers who have already successfully been through the Haste learning curve. In addition, the TiDE manual has been completely updated and includes more background material, particularly on optimization, timing validation and layout.