DAY 1: Basic language constructs; Introduction of the design flow

Training day from 9:00 till 17:00, including lunch and coffee/tea breaks.

 

Welcome

Introduction

  • General introduction
    • Asynchronous circuits in the world
    • Handshake Solutions
    • Technology advantages
  • Technical introduction
    • Haste and Handshake circuits
    • Handshake channels
    • Handshake Technology design flow

Sequential designs with variables – part 1

  • Sequential programming constructs
  • Types
  • Operators

Exercise 1: Arithmetic operation

  • Introduction
  • Exercise
  • Results

Sequential designs with variables – part 2

  • Conditional statements and expressions
  • Auxiliaries
  • Functions and procedures

Design flow overview

  • Hand in package (functional design)
  • Hand on package (modularity, optimization and DfT)
  • Hand over package (layout and timing validation)
  • NXP CoReUse structure

Exercise 2: GCD (Euclid's Greatest Common Divisor algorithm)

  • Introduction
  • Exercise
  • Results

 

DAY 2: Channels and non-handshaked communication; Simulation and the Verilog interface

Training day from 9:00 till 17:00, including lunch and coffee/tea breaks.

 

Design flow: Simulation

  • Simulation at different abstraction levels
  • Using the simulation viewer: htview
  • Inspecting simulation results without htview
  • Coverage simulation tool: htcover

Design flow: The Verilog interface

  • Creating a Haste Verilog netlist
  • Setting up a Verilog test bench
  • Using RAMs and ROMs
  • What is special about Haste Netlists
  • The design_sim file

Parallel designs with point-to-point channels

  • Parallel language constructs
  • Channel communication
  • Channel probing and choice statements
  • Several examples

Exercise 3a: Symbol width (3-to-8) converter

  • Using channels in parallel processes
  • Using the Verilog simulator

Non-handshake communications through wires

  • What are wires expressions, how to get them
  • Using wire expressions
  • Some design examples

Exercise 4: Clocked/Handshake converter

  • Communicating every clock tick
  • Not communicating every clock tick
  • Low(er) power implementation

Exercise or demonstration 5: Virtual dual-ported RAM

  • Using a standard RAM to mimic a dual-ported RAM

Design flow: Circuit optimization and backend flow

  • Overview of the design flow
  • Optimization in the TiDE tools
  • Technology selection
  • Backend optimization and layout flow

 

DAY 3: Advanced flow aspects and circuit background

Training day from 9:00 till 16:00, including coffee/tea break.

 

Design flow: using the linker

  • Modular design: importing and exporting
  • Linking at two levels: Haste level and Verilog (netlist) level
  • Htlink and the Haste netlist hierarchy
  • Htlink and the viewer tools: htview and htcover

Exercise 3b: Symbol width (3-to-8) converter

  • Using the linker: htlink

Circuit implementation and timing analysis

  • Implementation of some Handshake components
  • Components working together
  • Timing constraints

Scan testing using htscan

  • Introduction to the scan flow
  • Scan circuit background
  • Test integration

Reaching Handshake Solutions support

  • Contact information
  • Using the web interface

Exercise 6: I2C bus monitor

  • I2C bus-free monitor
  • I2C symbol converter (optional)