Introduction

Handshake Technology is a design methodology and associated toolset for clockless, self-timed circuits. The familiar global clock used in traditional very-large-scale-integration (VLSI) design is replaced with a system of request and acknowledgement signals or handshakes. Haste is Handshake Solutions' dedicated design entry language supporting CSP concepts like parallelism and channel communication. It is similar to the well-known C programming language and comparable with behavioral Verilog or VHDL. A Haste design is automatically translated to a standard Verilog netlist, which can be used to make a chip.

Simulation is a vital aspect in chip design. This can be done at different abstraction levels. For example at Verilog netlist level. To help the designer, simulation events must be translated back to the original Haste source code. This is done by the simulation viewer, htview.

Currently, htview uses a proprietary trace file format.

Goal of Project

The goal of this project is to investigate the usability of standard Verilog trace files (e.g. VCD files) to provide this feedback to the designer. Since the VCD file contains much more information, it becomes possible to provide much more information to the user. For example, displaying signals that are not in the Haste design, or signals that become undefined.

A main challenge of this assignment will be to find ways to efficiently deal with the huge amount of data that could be in a VCD file.

Candidate

This is an internship for a Computing Science or Electrical Engineering student. The ideal candidate has a background in simulators and user interface design using Motif and/or Xdesigner.