This package contains all the tools mentioned in the TIDE AE Lite package but maps all circuits onto a specific target library, allowing to balance performance, cost (chip area) and power consumption.

Additionally, this package includes the backend of the design flow, whose purpose is to generate the scripts to interface with third-party EDA tools to perform logic optimization on the netlists obtained by the compilation of Haste code. Furthermore it also allows retiming of the delay matchers to obtain a timing-optimal and correct netlist.

Finally, this package include the tools that generate the scripts to interface with third-party EDA tools to produce a layout of the netlist obtained by the compilation of Haste code.


TIDE AE contents:
Design tools (computer software) provided by Handshake Solutions with TIDE AE:

  • htcomp: Handshake Technology Compiler.
    Compiler that translates Haste source code to Handshake Circuits or directly to behavioral Verilog for fast simulation.

  • htsim: Handshake Technology Simulator.
    Simulator for Handshake Circuit level simulation.

  • htview: Handshake Technology Simulation viewer.
    Graphical viewer that links simulation results with the Haste source code. Works for simulation trace files, produced by htsim, or by the Verilog simulations (with monitors enabled).

  • htmap: Handshake Technology Mapper.Mapper/optimiser, which translates Handshake Circuits to Verilog netlists.

  • htlog: Handshake Technology Logic optimiser
    Tool that uses an external logic optimiser tool to perform optimisations and remapping of the netlist generated by htmap. Its main purpose is constant propagation.

  • htlink: Handshake Technology Linker.
    Linker for Verilog netlists (to support separate compilation).

  • htpost: Handshake Technology Post processor
    This tool prepares the hand over of the Handshake Solutions netlist to generic optimisation and layout tools (from external providers like Cadence and Synopsys). It generates scripts for optimisation and timing validation.


Documentation provided by Handshake Solutions with TIDE AE Lite:

  • Haste Language Manual
  • Handshake Solutions Design Flow Manual
  • Quick reference pages for each design tool

 

Required Operating System

TiDE AE is available for:

  • Red Hat Enterprise Linux WS

 

Required EDA Tools

TiDE AE requires a number of Third Party EDA tools to do circuit optimization, P&R, and verification.

 

For circuit optimisation and retiming:

  • Synopsys Design Compiler

For layout flow:

  • Cadence Encounter, or
  • Synopsys Astro + Synopsys Physical Compiler

For timing verification:

  • Synopsys PrimeTime