The design-entry language is a high-level programming language, called “Haste”. It supports parallelism and channel communication as inspired by Communicating Sequential Processes (CSP). A Haste program can be compiled to an asynchronous gate-level netlist, which uses a four-phase handshake protocol and single-rail data encoding (also known as bundled data). Simulation can be done at different levels of abstraction. The simulation traces can be linked back to the original Haste source.

This package also gives the option to map the Haste design onto a synchronous netlist, which can thereafter be used for prototyping the design on an FPGA.

TIDE AE Lite contents:
Design tools (computer software) provided by Handshake Solutions with TIDE AE Lite:

• htcomp: Handshake Technology Compiler.
  Compiler that translates Haste source code to Handshake Circuits or directly to behavioral Verilog for fast simulation.
  
  
• htsim: Handshake Technology Simulator.
  Simulator for Handshake Circuit level simulation.
  
  
• htview: Handshake Technology Simulation viewer.
  Graphical viewer that links simulation results with the Haste source code. Works for simulation trace files, produced by htsim, or by the Verilog simulations (with monitors enabled).
  
  
• htmap: Handshake Technology Mapper.
  Mapper/optimiser, which translates Handshake Circuits to Verilog netlist.
  
  

Documentation provided by Handshake Solutions with TIDE AE Lite:

• Haste Language Manual,
• Handshake Solutions Design Flow Manual,
• Quick reference pages for each design tool

Required Operating System

TiDE AE Lite is available for:

• Red Hat Enterprise Linux WS