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The HT80C51 is the Handshake Technology implementation of the ubiquitous 80C51 8-bit microcontroller. Functionally compatible with the original, the HT80C51 allows designers to leverage the vast existing software library available on the market. It is ideal for use in any 80C51 application, delivering improved performance at a significantly lower power level. This highly flexible block is capable of operating in either synchronous or asynchronous mode and is fully configurable with a growing range of peripheral functions.
- 2004-10-26T00:00:00.0000000-07:00For more information or to order products, simply contact us today!
- 2006-02-08T00:00:00.0000000-08:00HT80C51 User Manual
- 2005-03-16T00:00:00.0000000-07:00View webinar: "The ultra low-power HT80c51 microcontroller"
- 2006-02-08T00:00:00.0000000-08:00Download HT80C51 product brief
- 2007-03-30T00:00:00.0000000-07:00Download HT80C51 product brief (Japanese)
Applications
As with all Handshake Technology implementations, the HT80C51 boasts minimal operational power consumption, zero stand-by power and immediate wake-up. This enables the maximum functionality to be squeezed into even the tightest energy budget and ensures optimal performance at any system clock speed. Furthermore, very low electromagnetic emission (EME) levels and current peaks enable easy integration with RF and analog circuitry.
The HT80C51 delivers unique benefits to any application where a clocked 80C51 core can be used, particularly when power consumption or electromagnetic interference is an important issue. Handshake Technology implementations of the 80C51 have been used in numerous ICs across various markets including wireless, smart card and automotive.
Key features
- Extremely low power consumption, less than 90 pJ per instruction in a 0.18µ CMOS process
- Very low electromagnetic emission
- Supply current peaks at least a factor of five lower than clocked alternative
- Configurable core with a range of 80C51 peripherals and customizable memory interfaces
- Both core and peripherals consume zero power in idle mode yet
immediately respond to interrupts - Can operate in asynchronous or synchronous mode, controlled via a dedicated input that can be changed at run-time:
- in asynchronous mode the CPU runs at its natural speed and is not affected by a system clock
- in synchronous mode the CPU synchronizes to the clock such
that the number of clock cycles per instruction is the same as the
number of machine cycles for a clocked implementation
Modules
The HT80C51 implementation is functionally compatible with the existing 80C51 instruction set and peripherals. Numerous core and peripheral modules are available, including:
- HT80C51 CPU
- with optional dual data pointers and MOVC code protection
- Interrupt controller with up to 15 interrupt lines
- Timers 0 and 1
- UART, I2C and SPI interfaces
- DES and triple-DES module
- Handshake Technology peripheral bus
- Synchronous peripheral bus bridge
Further peripheral functions are being developed, and specific
modules can be implemented on demand.
Delivery
The HT80C51 delivery comprises a netlist and scripts for standard EDA tools from supported tool vendors (Synopsys, Cadence, Magma and Mentor). Special tools for asynchronous logic are not required.
- A firm netlist with the HT80C51 design mapped onto the customerselectedstandard-cell library, including scan chains, if selected
- Various scripts and constraint files for use with standard EDA tools
- Place and Route (P&R), Automatic Test Pattern Generation (ATPG), Static Timing Analysis (STA), Logic Equivalence Checking (LEC) and simulation
- A sample test figure with signal checkers, easily integrated into a system test fixture
- An optional netlist for easily mapping onto FPGAs for prototyping
HT80C51 subsystem
Software development
As the HT80C51 is fully compatible with standard 80C51 controllers, any 80C51 software development suite can be used. Specically, the HT80C51 is supported by:
- µVision IDE from Keil Software (See Keil web site)
- An optional debug interface, compatible with First Silicon Solutions' On-chip Instrumentation (OCITM) interface for embedded emulation via JTAG (see FS2 web site)
Characterization
The following table compares power and performance figures for fully scan-testable cores at 25 °C and 1.8 V operating voltage, manufactured in a typical 0.18 µm CMOS process.
| Area | Performance1 | Power consumption | |||
| Geq4 | MIPS | MHz | pJ/instruction | μW/MHz | |
| HT80C51 | 5500 | 9.2 | 88.02 | 89 | 9.3 |
| Clocked 80C513 | 5600 | 4.8 | 46.0 | 500 | 52.0 |
1Average execution time of an 80C51 instruction is 1.6 machine cycles (9.6 clock cycles)
2Equivalent performance assuming 6 clock cycles per machine cycle
3Synchronous implementation of an 80C51 with 6 clock cycles per machine cycle
4Gate equivalents - area in terms of basic 2-input NAND gates
Power consumption of a clocked (left) and Handshake Technology (right) 80C51 microcontroller executing the same program. The upper waveforms show the current consumption in the time domain, the lower diagrams show the transformation into the frequency spectrum. The HT80C51 produces much lower current peaks, has lower average current consumption and the spectrum is limited to low frequencies.
