The HT80C51MX is the first clockless implementation of the 80C51MX(Memory eXtension) core. It combines the low power and easy system integration of Handshake Technology with the extended memory capabilities of the MX architecture to create an extremely versatile microcontroller core. Backwards compatible with the HT80C51 and functionally equivalent to clocked versions, it provides a seamless upgrade path for more advanced 8-bit applications.

 

The MX architecture extends the memory addressing capabilities of 80C51 cores to a maximum of 8 Mbytes of program and 8 Mbytes of data memory. The memory is accessed using a linear, non-segmented approach, eliminating inefficient bank-switching solutions when crossing 64-Kbyte boundaries. The HT80C51MX features a number of additional instructions to allow full use of the
extended memory addressing. A new Universal Pointer addressing mode also enables any area of memory to be accessed with a single instruction so high-level language compilers can easily optimize code for size and execution time.


As with all Handshake Technology implementations, the HT80C51MX boasts minimal operational power consumption, zero standby power and immediate wake-up. This enables the maximum functionality to be squeezed into even the tightest energy budget and ensures optimal performance at any system clock speed. Furthermore, it produces very low electromagnetic emission (EME) levels and current peaks enabling easy integration with RF and analog circuitry. The core can run in either asynchronous or synchronous mode, maintaining all the benefits of Handshake Technology in both.

  1. 2004-10-26T00:00:00.0000000-07:00For more information or to order products, simply contact us today!
  2. 2007-09-19T00:00:00.0000000-07:00Download HT80C51MX product brief
  3. 2007-09-25T00:00:00.0000000-07:00Download HT80C51MX product brief (Japanese)

Key features

  • Configurable, clockless 80C51MX (Memory eXtension) core
  • Supports up to 8 Mbytes program and 8 Mbytes data memory
    - Linear, non-segmented access for maximum performance
  • Enhanced high-level language performance and efficiency
  • Extremely low power consumption, EME and current peaks
  • Range of 80C51 peripherals available
  • Both core and peripherals consume zero power in idle mode yet immediately respond to interrupts
  • Can operate in asynchronous or synchronous mode, controlled via a dedicated input that can be changed at run-time:
    - in asynchronous mode the CPU runs at its natural speed and is not affected by a system clock
    - in synchronous mode the CPU synchronizes to the clock such that the number of clock cycles per instruction is the same as the number of machine cycles for a clocked implementation

Applications

The HT80C51MX is ideally suited to use in smart card designs. However, it also delivers unique benefits in any application where a traditional 80C51 core can be used, particularly where power consumption or electromagnetic interference is an important issue. Its extended memory capabilities offer designers a cost-effective route to new, more complex 8-bit applications using the familiar 80C51 architecture

Modules

The HT80C51MX implementation is functionally compatible with the existing 80C51 instruction set and peripherals. Numerous core and peripheral modules are available, including:

  • HT80C51MX CPU
    - with optional dual data pointers and MOVC code protection
  • Interrupt controller with up to 15 interrupt lines
  • Timers 0 and 1
  • UART, I2C and SPI interfaces
  • DES and triple-DES module
  • Handshake Technology peripheral bus
  • Synchronous peripheral bus bridge
  • General-purpose I/Os

Further peripheral functions are being developed, and specific modules can be implemented on demand.

Delivery

The HT80C51MX delivery comprises a netlist and scripts for standard EDA tools from supported tool vendors (Synopsys, Cadence, Magma and Mentor Graphics). No special tools for asynchronous logic are required.

  • A firm netlist with the HT80C51MX design mapped onto the customer-selected standard-cell library, including scan chains, if selected
  • Various scripts and constraint files for use with standard EDA tools
    - Place and Route (P&R), Automatic Test Pattern Generation (ATPG), Static Timing Analysis (STA), Logic Equivalence Checking (LEC) and simulation
  • A sample test fixture with signal checkers, easily integrated into a system test fixture
  • An optional netlist for easily mapping onto FPGAs for prototyping

Furthermore, the HT80C51MX is completely backwards compatible with the HT80C51. So any code written for the HT80C51 can be run on the HT80C51MX with no changes.

 

HT80C51MX subsystem

Software development

As the HT80C51MX is fully compatible with standard 80C51 controllers, any 80C51 software development suite can be used. Specifically, the HT80C51MX is supported by:

  • μVision IDE from Keil Software
  • An optional debug interface, compatible with First Silicon Solutions' On-chip Instrumentation (OCI™) interface for embedded emulation via JTAG (see | FS2 web site)

 

Characterization

The following table compares power and performance figures for cores at 25oC and 1.8V operating voltage, manufactured in a typical 0.14um CMOS process with no scan test being implemented

 

  Area Performance Power Code size Data size Internal data
  kilogates* MIPS pJ per instruction maximum for code memory maximum for data memory maximum internal data memory
HT80C51 4.0 12 74 64 kB 64 kB 256 B
HT80C51MX 9.1 16 101 8 MB 8 MB 64 kB

* in terms of 2-input NAND gates

 

 

Downloads

  1. 2007-09-19T00:00:00.0000000-07:00HT80C51MX product brief
  2. 2007-09-25T00:00:00.0000000-07:00HT80C51MX product brief (Japanese)