Imagine an interconnect that runs when you need it, and happily sits idle when you don't. That is exactly what you get with the HTmAHB interconnect. With no clock needed, this interconnect cuts power consumption at the system level, simplifies timing closure and eliminates idle cycles and wait states. The natural fit for clockless 32-bit ARM cores, it can also be used with traditional clocked systems.

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  1. 2007-04-16T00:00:00.0000000-07:00HTmAHB Interconnect product brief

 

The HTmAHB interconnect is a clockless implementation of the multilayer ARM® AMBA™ AHB - an interconnect scheme that enables parallel access paths between multiple masters and slaves. It is compatible with clockless and clocked masters and slaves, enabling maximum IP re-use. It can also bridge to synchronous data transfer protocols such as the ARM® AMBA™ APB.

Like all Handshake Technology implementations, the HTmAHB interconnect boasts low power consumption, low electromagnetic emission (EME) and zero standby power with immediate wake up. It is compatible with standard EDA tools and standard cell libraries. Furthermore, it is fully scan-testable.

Applications
The HTmAHB interconnect is ideal wherever power, electromagnetic emission and robustness are key issues. It is aimed at medium-performance systems and is particularly suited to event- or interrupt-driven applications.

Key features

  • Clockless multilayer AHB
  • Low power consumption
  • Low electromagnetic emission
  • Simplifies timing closure
  • Eliminates wait states and idle cycles
  • Low latency without the need for a fast clock
  • Compatible with clocked and clockless masters and slaves
  • Automatically adapts to each master and slave ensuring optimal
  • data transfer
  • Highly configurable with numerous options

 

Options
You can configure the HTmAHB interconnect to suit your particular needs by specifying the:

  • number of masters
  • interface (synchronous or asynchronous) for each master
  • number of ports
  • number of slaves for each port
  • interface (synchronous or asynchronous) for each slave
  • address map

 

Delivery
The HTmAHB interconnect delivery is fully compatible with standard EDA tools, so no specialized asynchronous tools or knowledge are required. The delivery comprises:

  • A firm netlist of the HTmAHB interconnect design mapped onto a customer-selected standard-cell library
    • Includes Design-for-Test solution based on scan testing
  • Test patterns for embedded scan test and the re-model files to enable the generation of the patterns
  • Various scripts and constraint files for use with standard EDA tools
    • Place and Route (P&R),
    • Automatic Test Pattern Generation (ATPG),
    • Static Timing Analysis (STA),
    • Logic Equivalence Checking (LEC) and
    • Simulation
  • An optional netlist for easy mapping onto FPGAs for prototyping

 

Characteristics
The exact characteristics of the HTmAHB interconnect vary with the options and technology chosen. For a configuration with 2 masters, 3 slaves and 2 ports in a 0.13-μm process, the interconnect is about 2400 gates (comparable to a clocked implementation) and runs at around 100 MHz. Zero active standby power helps reduce
system-level power consumption, especially in systems with many IDLE / WAIT cycles.

 

 

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  1. 2007-04-16T00:00:00.0000000-07:00HTmAHB Interconnect product brief