The design flow is based on standard-cell libraries and allows you to create clockless designs without dedicated asynchronous standard cells. TiDE supports both scan-test-based Design-for-Test and FPGA prototyping.

Key features

• Easy-to-use design flow for clockless design
• Extension of existing third-party EDA flows supporting complete design process from entry to layout
• Targeted at your preferred toolset e.g. Cadence, Synopsys, Magma, Mentor Graphics, etc.
• Supports scan-based Design-for-Test and FPGA prototyping
• Based on standard-cell libraries with no dedicated cells needed
• Uses standard EDA tools for:
• Logic optimization
• Test-pattern generation
• Placement and routing
• Timing verification
• Formal verification
• Signal-integrity analysis
• Simulation
• Supports integration with synchronous blocks and systems
• Academic versions (TiDE AE and TiDE AE Lite) are available within the Academic Program

Latest releases

TiDE is a robust and mature design environment that has been in use for many years. To further improve design efficiency and ensure TiDE continues to meet your evolving needs, we release updated versions with enhanced functionality approximately twice a year.

1. 2007-04-17T00:00:00.0000000-07:00The most recent TiDE release

Some frequently asked questions

Does the whole design have to be done in TiDE?
Not necessarily. Most Handshake Technology-based products on the market today combine blocks that were created both with and without TiDE. In some cases, synchronous blocks were incorporated into Handshake Technology blocks. In others, a Handshake Technology block was incorporated in a larger synchronous design.

Can TiDE translate a clocked design into a Handshake Technology design?
Methods are known to translate clocked designs into clockless designs directly. However these translations do not offer the main benefit associated with Handshake Technology: reduced energy consumption. In addition, these circuits tend to be larger. This is mainly due to the starting point (e.g. register-transfer level or gate-level netlist), where design choices dictated by synchronous implementation have already been made. To achieve the performance with a clockless design it is better to start from a higher level specification.

Does Handshake Technology lead to an area penalty?
Handshake Technology circuits typically occupy the same area (that is ±10%) as clocked equivalents. Primarily this is due to the use of so-called single-rail datapaths, which use the same combinational logic from the same standard-cell libraries as synchronous circuits. What’s more, because of the reduced current peaks of Handshake Technology circuits, the need for large buffer zones in the integration with analog and RF parts is reduced or eliminated. This often leads to cost (area) savings at system level.

Downloads and Further Links

1. 2004-01-01T00:00:00.0000000-08:00TiDE product brief