TiDE is an all-in-one suite of easy-to-use tools for designing and optimizing clockless circuits using Handshake Technology. Compatible with standard EDA toolsets, it offers designers a high degree of familiarity.

The design flow is based on standard-cell libraries and allows you to create clockless designs without dedicated asynchronous standard cells. TiDE supports both scan-test-based Design-for-Test and FPGA prototyping.

 

Key features

  • Easy-to-use design flow for clockless design
  • Extension of existing third-party EDA flows supporting complete design process from entry to layout
    • Targeted at your preferred toolset e.g. Cadence, Synopsys, Magma, Mentor Graphics, etc.
  • Supports scan-based Design-for-Test and FPGA prototyping
  • Based on standard-cell libraries with no dedicated cells needed
  • Uses standard EDA tools for:
    • Logic optimization
    • Test-pattern generation
    • Placement and routing
    • Timing verification
    • Formal verification
    • Signal-integrity analysis
    • Simulation
  • Supports integration with synchronous blocks and systems
  • Academic versions (TiDE AE and TiDE AE Lite) are available within the Academic Program

 

The TiDE toolset

  • Handshake Technology compiler (htcomp)
  • Handshake Technology mapper (htmap)
  • Handshake Technology simulator (htsim)
  • Handshake Technology viewer (htview)
  • Handshake Technology code coverage tool (htcover)
  • Handshake Technology linker (htlink)
  • Handshake Technology logic optimizer (htlog)
  • Handshake Technology scan-chain inserter (htscan)
  • Handshake Technology post processor (htpost)
  • Handshake Technology remodel file generator (htremodel)

 

Further Information

  1. 2008-01-24T00:00:00.0000000+01:00Functional design in TiDE™
  2. 2008-01-24T00:00:00.0000000+01:00Structural design in TiDE™
  3. 2008-01-24T00:00:00.0000000+01:00Physical design in TiDE™
  4. 2007-04-17T00:00:00.0000000+02:00Haste Design Language
    Haste is Handshake Solutions high-level design language developed specifically for the design-entry stage of clockless IC design.

Downloads and Further Links

  1. 2004-01-01T00:00:00.0000000+01:00TiDE product brief