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The physical part of the TiDE design flow is based entirely on standard third-party EDA tools. The generated constraint files and scripts included in TiDE control the operation of these tools, ensuring they carry out the following tasks correctly.
- Margin evaluation and delay tuning
- Loop breaking to support timing analysis
- Identification and fixing of large-fanout nets
- Set-up and hold-time checking
- Timing sign-off
- Signal-integrity analysis
Verification
TiDE supports formal verification between the structural Verilog netlists all the way from the initial htmap netlist to the final post-layout netlist. Formal verification is carried out with standard verification tools. Equivalence checking of a design that is mapped onto different target technologies is also supported.