As TiDE supports modular design, different Haste programs can be compiled separately and linked at a later point using htlink . This tool can also link in combinational blocks (such as multipliers) generated using datapath compilers, putting a handshake wrapper around such blocks to ensure they are correctly integrated throughout the flow.

After linking, htlog can be used for ‘peephole optimization’ at integration boundaries, for example when constant propagation is needed to remove inefficiencies. This tool relies on familiar, third-party logic optimization tools, instructing them which optimizations are required and allowed for various parts of the Handshake Technology netlist.

Design-for-Test (DfT) infrastructure can be added by htscan , which implements a full scan solution for the datapath and control elements. This unique approach for clockless design provides similar coverage levels to those for synchronous designs. Furthermore, TiDE’s htremodel can be used during physical design to generate remodel files of the post-layout netlist that are compatible with standard automatic test-pattern generation (ATPG) tools. This process supports detailed coverage analysis plus fault location for any faults found during production testing.

Hand-off to the physical design stage of the flow is based on a combination of standard Synopsys Design Constraints (SDC) and proprietary Handshake Constraint Format (HCF) files generated by htpost . TiDE also includes TCL scripts for translating the HCF file into operations and constraints for third-party physical design tools.